The present invention relates to integrated circuit manufacture and, more particularly, to the transfer and loading of semiconductor wafers into and out of processing chambers.
The fabrication of integrated circuit devices often involves a complex interplay of photolithography, etching, plasma deposition and chemical vapor deposition (CVD) processes. Technological development has yielded advances in all areas of semiconductor integrated circuit manufacturing and design. Reductions in circuit size allow increasing numbers of circuits to be placed upon an individual semiconductor wafer. Refined processes permit circuit layers to be deposited and etched within shorter times. These technological breakthroughs have dramatically increased the manufacturing throughput of circuit devices: more devices can be made in less time.
Increased throughput, however, places enormous demands upon the support infrastructure of integrated circuit processing systems. The quantity and speed of processing tend to magnify any delays which occur along the processing path. In particular, the transport system for moving semiconductor wafers into and out of processing chambers has become a bottleneck in the fabrication cycle. Present etching processes may last only 120 seconds. Newer processes take as little as 60 to 80 seconds per wafer. Since the transport process itself can require 100 to 120 seconds per wafer, manufacturing efficiency is lost as processing chambers sit idle waiting for reloading.
Newer fabrication systems cluster multiple processing chambers around a central airlock area where holders of to-be-processed wafers are brought into and out of the processor, only exacerbating the wafer transportation problem. A transport arm brings each wafer to its proper processing chamber and upon process completion retrieves the wafer back to its holder. When the transport system cannot keep up with the rapid processing of wafers in each of the clustered chambers, further backups occur and total output suffers.
What is needed is an improved method and system for carrying semiconductor wafers to and from processing chambers. The method and system should rapidly load and unload wafers from individual chambers, while maintaining precision and safety. In addition, the method and system should remain adaptable to a wide variety of processing environments and should readily handle multiple chambers without producing undesirable slowdowns and bottlenecks.